In current complementary metal oxide semiconductor (CMOS) technology, MOSFET devices having a minimum effective gate length of about 0.25 .mu.m atop a 5 nm thin gate oxide with a 100 nm deep source/drain junction can be fabricated. Future generations of CMOS technology will ultimately require sub-0.1 .mu.m gate lengths and a source/drain junction depth of less than 20 nm in order to obtain faster switching speeds and denser packing requirements while avoiding short channel effects. Attempts to extend present CMOS technology to achieve these objectives have been unsatisfactory largely due to the difficulty in forming a shallow junction with a steep dopant profile having a three or four decade change in concentration over a short distance of 2-3 nm. Another problem is the consumption of silicon (Si) which occurs during silicidation for source/drain contacts. This Si consumption typically occurs when the junction is too shallow.
One alternative MOSFET structure to solve these problems is a raised source/drain MOSFET structure which requires a selective epitaxial Si growth to form the source and drain regions. To grow high quality single crystalline Si, the prior art Si epi-processes utilize a high temperature (greater than 900.degree. C.) pre-cleaning step wherein the dopant species moves. This movement of dopant species within the structure influences the critical dopant profile.
Another alternative structure employed in the prior art to avoid the above drawbacks is a recessed channel/gate MOSFET, in which the recessed channel is defined by thermal oxidation. The use of thermal oxidation creates a bird-beak as well as leading to difficulties in controlling the critical dimension of the channel.
In order to succeed at sub-0.1 .mu.m gate dimensions and below it will be necessary to develop new CMOS technology that circumvents all of the problems mentioned hereinabove.